Single chip digital signal processing devices (DSP) are relatively well known. DSPs generally are distinguished from general purpose microprocessors in that DSPs typically support accelerated arithmetic operations by including a dedicated multiplier and accumulator (MAC) for performing multiplication of digital numbers. The instruction set for a typical DSP device usually includes a MAC instruction for performing multiplication of new operands and addition with a prior accumulated value stored within an accumulator register. A MAC instruction is typically the only instruction provided in prior art digital signal processors where two DSP operations, multiply followed by add, are performed by the execution of one instruction. DSPs are often programmed in a loop to continuously perform a MAC instruction using different operands. An area where DSPs may be utilized is in telecommunication systems. One use of DSPs in telecommunication systems is digital filtering. In this case a DSP is typically programmed with instructions to implement some filter function in the digital or time domain. The mathematical algorithm for a typical finite impulse response (FIR) filter may look like the equation Y.sub.n =h.sub.0 X.sub.0 +h.sub.1 X.sub.1 +h.sub.2 X.sub.2 +. . . +h.sub.N X.sub.N where h.sub.n are fixed filter coefficients numbering from 1 to N and X.sub.n are the data samples. The equation Yn may be evaluated by using a software program. However in some applications, it is necessary that the equation be evaluated as fast as possible. One way to do this is to perform the computations using hardware components such as a DSP device programmed to compute the equation Yn. In order to further speed the process, it is desirable to vectorize the equation and distribute the computation amongst multiple DSPs such that the final result is obtained more quickly. The multiple DSPs operate in parallel to speed the computation process. In this case, the multiplication of terms is spread across the multipliers of the DSPs equally for simultaneous computations of terms. The adding of terms is similarly spread equally across the adders of the DSPs for simultaneous computations. In vectorized processing, the order of processing terms is unimportant since the combination is associative. If the processing order of the terms is altered, it has no effect on the final result expected in a vectorized processing of a function.
However, not all computations of equations can be vectorized. This is the case with some of the standardized compression/decompression algorithms used in telecommunication systems. In this case, the computation processes typically can not be performed in parallel by standard DSPs. A nonvectorizable equation usually must be processed in a specific manner due to some constraints. Exemplary of this is the voice compression and voice decompression ITU standards used in coder/decoders (CODECs). Specifically, this includes the ITU standards G.723.1, G.728, and G.729. In equations for these functional operations, sixteen bit fixed point arithmetic is utilized. In order to be compliant with the standards, operations found within the specification must be carried out exactly in order to maintain signal quality. Additionally, the bits must be exact and the saturation must be carried out appropriately. Four terms of a typical nonvectorizable equation where nonvectorized processing is required, are YOUTn=((((AC+.sub.L a.sub.0 X.sub.0)+.sub.L a.sub.1 X.sub.1)+.sub.L a.sub.2 X.sub.2)+.sub.L a.sub.3 X.sub.3) where "+.sub.L " refers to a limiting of the addition to a range of values between a positive saturation value and a negative saturation value and AC is an accumulated value for a prior processing cycle. A typical DSP device needs to process each term separately from inner brackets to outer brackets. One disadvantage to processing in this fashion is that the extra processing steps require additional cycles. The additional cycles decrease the channel handling capability of a DSP device thereby requiring that additional DSP devices be used to increase the channel handling capability. Additionally, in a multiple DSP system, a number of DSPs may be sitting idle awaiting completion of the term presently being computed by the active DSP. This is an inefficient use of computing resources.
Additionally, the quality of service over a telephone system often relates to the processing speed of signals. That is particularly the case when a DSP is to provide voice processing, such as voice compression, voice decompression, and echo cancellation for multiple channels. More recently, processing speed has become even more important because of the desire to transmit voice aggregated with data in a packetized form for communication over packetized networks. Delays in processing the packetized voice signal tend to result in the degradation of signal quality on receiving ends.
It is desirable to provide improved processing of voice and data signals to enhance the quality of voice and data communication over packetized networks. It is desirable to improve the efficiency of using computing resources when performing signal processing functions.